Portal de Transparencia

Actividad investigadora:

• Artículos en revistas
  • [2019] Artificial Vision on Edge IoT Devices: A Practical Case for 3D Data Classification
  • [2019] Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems
  • [2019] Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems
  • [2018] A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images
  • [2018] FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo(3) Framework
  • [2018] IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado
  • [2018] Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale plus Hardened Processing Fabrics
  • [2017] Dynamic Reconfiguration under RTEMS for Fault Mitigation and Functional Adaptation in SRAM-based SoPCs for Space Systems
  • [2016] A scalable H.264/AVC deblocking filter architecture
  • [2015] Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis
  • [2014] Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic
  • [2013] A scalable H.264/AVC Deblocking Filter Architecture
  • [2013] A scalable H.264/AVC Deblocking Filter Architecture
  • [2013] Architectural Evaluation of Dynamic and Partial Reconfigurable Systems designed with DREAMS Tool
  • [2013] Sophisticated Security Verification on Routing Repaired Balanced Cell-Based Dual-Rail Logic against Side Channel Analysis
  • [2013] Sophisticated Security Verification on Routing Repaired Balanced Cell-Based Dual-Rail Logic against Side Channel Analysis
  • [2012] Automatic Generation of Identical Routing Pairs for FPGA Implemented DPL Logic
  • [2012] Dreams: A Tool for the design of Dynamically Reconfigurable Embedded and Modular Systems
  • [2012] Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks
  • [2010] Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors
  • [2010] Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors
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• Capítulos de libros
  • [2014] 13.13 Wireless Sensor Networks: From Real World to System Integration ? Alternative Hardware Approaches
  • [2012] Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC and SVC Video Codecs
• Estancias y sabáticos recogidos en programas oficiales
  • [2011] Estancia para la realización de tesis
• Ponencia en Congresos
  • [2019] A Fast Prototyping Workflow for Reconfigurable SDR Applications
  • [2019] Artificial Vision on Edge IoT Devices: A Practical Case for 3D Data Classification
  • [2019] Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems
  • [2019] Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems
  • [2019] Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems
  • [2018] 'Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale+ Hardened Processing Fabrics'
  • [2018] IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado
  • [2014] Increased fault tolerance in evolvable hardware through automatic upscaling
  • [2013] A Noise-Agnostic Self-Adaptive Image Processing Applications Based on Evolvable Hardware
  • [2013] A Noise-Agnostic Self-Adaptive Image Processing Applications Based on Evolvable Hardware
  • [2013] A Novel FPGA-based Evolvable Hardware System based on Multiple Processing Arrays
  • [2013] A Novel FPGA-based Evolvable Hardware System based on Multiple Processing Arrays
  • [2013] A Scalable Evolvable Hardware Processing Array
  • [2013] A self-adaptive image processing application based on evolvable and scalable hardware
  • [2013] Architectural Evaluation of Dynamic and Partial Reconfigurable Systems designed with DREAMS Tool
  • [2013] Architectural Evaluation of Dynamic and Partial Reconfigurable Systems designed with DREAMS Tool
  • [2013] Noise-agnostic Adaptive Image Filtering without Training References on an Evolvable Hardware Platform
  • [2012] Automatic Generation of Identical Routing Pairs for FPGA Implemented DPL Logic
  • [2012] Dreams: A Tool for the design of Dynamically Reconfigurable Embedded and Modular Systems
  • [2012] Implementation techniques for evolvable HW systems: virtual vs. dynamic reconfiguration
  • [2012] Implementation techniques for evolvable HW systems: virtual vs. dynamic reconfiguration
  • [2012] On The Automatic Integration of Hardware Accelerators into FPGA-based Embedded Systems
  • [2011] "Scalable 2D architecture for H.264 SVC deblocking filter with reconfiguration capabilities for on-demand adaptation"
  • [2011] 2D Reconfigurable Systolic Core Architecture for Evolvable Systems
  • [2011] A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self- Adaptive Systems
  • [2011] A Novel Scalable Deblocking-Filter Architecture for H.264/AVC and SVC Video Codecs
  • [2011] Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs
  • [2011] Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support
  • [2011] Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems
  • [2011] Framework adaptable y reconfigurable dinámicamente para procesamiento de vídeo: aplicación a la etapa de filtrado adaptativo en sistemas de compresión de vídeo H.264/AVC y SVC
  • [2011] Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs
  • [2010] A Modular Peripheral to Support Self¿Reconfiguration in SoCs
  • [2010] Feasibility of HW genetic algorithms for profile selection in reconfigurable autonomous embedded systems
  • [2010] Generic Systolic Array for Run-time Scalable Cores
  • [2010] Run-time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs
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• Premios
  • [2012] Best Paper Award
  • [2012] Best paper award
• Proyectos de I+D+i
  • [2018] GORDON 2.0: DESARROLLO HERRAMIENTA SOFTWARE DE RESPUESTA EN TIEMPO REAL PARA OPTIMIZAR UNA FLOTA DE RECOGIDA SOSTENIBLE (GORDON 2.0)
  • [2018] PLATINO: Plataforma HW/SW distribuida para el procesamiento inteligente de información sensorial heterogénea en aplicaciones de supervisión de grandes espacios naturales
  • [2016] ENABLE-S3: European Initiative to Enable Validation for Highly Automated Safe and Secure Systems
  • [2015] DREAMS-UPM: Dynamically Reconfigurable embedded platforms for Networked Context-aware multimedia Systems-UPM
  • [2014] FastCUDA
  • [2012] DYNAMICALLY RECONFIGURABLE EMBEDDED PLATFORM FOR NETWARKED CONTEXT-AWARE MULTIMEDIA SYSTEMS-UPM
  • [2011] DYNAMICALLY RECONFIGURABLE EMBEDDED PLATFORM FOR NETWARKED CONTEXT-AWARE MULTIMEDIA SYSTEMS-UPM
  • [2011] FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels
  • [2011] RECONFIGURABILIDAD DINAMICA PARA ESCALABILIDAD EN REDES ORIENTADAS A APLICACIONES MULTIMEDIA
  • [2011] RECONFIGURABILIDAD INTEROPERABLE
  • [2011] RECONFIGURABLE ULTRA-AUTONOMOUS NOVEL ROBOTS RUNNER
  • [2010] RECONFIGURABILIDAD DINAMICA PARA ESCALABILIDAD EN REDES ORIENTADAS A APLICACIONES MULTIMEDIA
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• Responsabilidades
  • [2012] Miembre del Program Committeee de Reconfig 2012
  • [2012] Miembro del Program Committee de ERSA 2012
  • [2012] Miembro del Program Committee de SPL 2012
  • [2012] Revisor de DATE 2012
  • [2012] Revisor de Int Conf on Field Programmable Logic and Applications (FPL) 2012
  • [2012] Revisor de Transactions on Evolutionary Computation
  • [2012] Revisor en 2012 International Conference on ReConFigurable Computing and FPGAs (ReConFig2012)
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• Tesis Doctorales
  • [2014] Run-Time Scalable Hardware for Reconfigurable Systems
  • [2013] Noise-agnostic self-adaptive evolvable hardware for real time video filtering applications