Portal de Transparencia

Actividad investigadora:

• Artículos en revistas
  • [2019] Artificial Vision on Edge IoT Devices: A Practical Case for 3D Data Classification
  • [2019] Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems
  • [2019] DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping
  • [2019] DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping
  • [2019] Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems
  • [2019] Hardware Accelerator for Ethanol Detection in Water Media based on Machine Learning Techniques
  • [2019] Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression
  • [2018] A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images
  • [2018] FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo(3) Framework
  • [2018] IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado
  • [2018] Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems
  • [2018] On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming
  • [2018] On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming
  • [2017] Analysis of a Heterogeneous Multi-Core, Multi-HW-Accelerator-Based System Designed Using PREESM and SDSoC
  • [2017] Cross-layer Design of Reconfigurable Cyber-Physical Systems
  • [2017] Dynamic Reconfiguration under RTEMS for Fault Mitigation and Functional Adaptation in SRAM-based SoPCs for Space Systems
  • [2016] A scalable H.264/AVC deblocking filter architecture
  • [2016] Introduction to the Special Section on FPGAs Technology and Applications
  • [2016] Teaching Hybrid HW/SW Embedded System Design Using FPGA-Based Devices
  • [2015] Introduction to Special issue on Reconfigurable computing and FPGAs
  • [2015] Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis
  • [2014] A Run Time Adaptive Architecture to trade-off Performance for Fault Tolerance applied to a DVB On-Board Processor
  • [2014] Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic
  • [2014] Introduction to Special issue on FPGA Devices and Applications
  • [2014] Introduction to the special issue on FPGA Technology and Applications
  • [2014] Power-Aware Multi-Objective Evolvable Hardware System on an FPGA
  • [2013] A scalable H.264/AVC Deblocking Filter Architecture
  • [2013] A scalable H.264/AVC Deblocking Filter Architecture
  • [2013] Architectural Evaluation of Dynamic and Partial Reconfigurable Systems designed with DREAMS Tool
  • [2013] Sophisticated Security Verification on Routing Repaired Balanced Cell-Based Dual-Rail Logic against Side Channel Analysis
  • [2013] Sophisticated Security Verification on Routing Repaired Balanced Cell-Based Dual-Rail Logic against Side Channel Analysis
  • [2012] Automatic Generation of Identical Routing Pairs for FPGA Implemented DPL Logic
  • [2012] Dreams: A Tool for the design of Dynamically Reconfigurable Embedded and Modular Systems
  • [2012] Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks
  • [2011] Embedded Runtime Reconfigurable Nodes for Wireless Sensor Networks Applications
  • [2010] Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors
  • [2010] Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors
  • [2010] Reconfigurable Networks on Chip: DRNoC architecture
  • [2007] A digital system to emulate wireless networks
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• Capítulos de libros
  • [2014] 13.13 Wireless Sensor Networks: From Real World to System Integration ? Alternative Hardware Approaches
  • [2012] Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC and SVC Video Codecs
  • [2011] FPGAs and reconfigurable systems
  • [2010] Dynamic Reconfigurable NoC (DRNoC) Architecture: Application to Fast NoC Emulation
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• Conferencias invitadas en congresos
  • [2019] Heterogeneous Cyber Physical Systems of Systems
  • [2018] Tutorial on Adaptive and Secure Ctber-Physical Systems
  • [2017] Self-Adaptation of Cyber Physical Systems: Flexible HW/SW computing
  • [2016] Hardware Adaptation by Means of DPR: How and What for?
  • [2016] Partial Reconfiguration aspplied to Dynamic Multihread Hardware Acceleration and Evolvable Hardware
  • [2016] Towards Smarter Reconfigurable Systems
  • [2011] International Conference on Reconfigurable Computing and FPGAs (ReCOnFig), 2011
  • [2011] International Society for Optics and Photonics, VLSI Circuits and Systems
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• Cursos, seminarios y tutoriales
  • [2018] Self-adaptivity in heterogeneous CPS platforms
• Estancias y sabáticos recogidos en programas oficiales
  • [2018] Integración de aceleradores HW en herramienta PREESM, gestión dinámica (Spider) y monitorización de energía prestaciones y fallos (interfaz API de ARTIo3)
  • [2013] Estancia Postdoctoral. Roland Dobai
  • [2010] Estancia de Teresa Cervero (Universidad de Las Palmas)
  • [2010] Estancia de Teresa Cervero (Universidad de Las Palmas)
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• Libros
  • [2017] FPGAs. Fundamentals, Advanced Features and Applications in Industrial electronics
  • [2014] FPGA-Based High Performance Wireless Sensor Node
  • [2013] 2013 International Conference on ReConFigurable Computing and FPGAs
  • [2012] 2012 International Conference on ReConFigurable Computing and FPGAs
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• Otras Publicaciones
  • [2015] Introduction to Special issue on Reconfigurable computing and FPGAs
  • [2015] Letter from the guest editors of the special issue on DCIS 2014
  • [2012] 2012 International Conference on ReConFigurable Computing and FPGAs
• Otros méritos
  • [2014] Premio FFII al mejor Proyecto Fin de Carrera de 2014
  • [2011] Editor Microtechnologies for the New Millennium 2011
• Ponencia en Congresos
  • [2019] Artificial Vision on Edge IoT Devices: A Practical Case for 3D Data Classification
  • [2019] Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems
  • [2019] Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems
  • [2019] Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems
  • [2019] Hardware Accelerator for Ethanol Detection in Water Media based on Machine Learning Techniques
  • [2019] Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach
  • [2019] Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach
  • [2018] 'Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale+ Hardened Processing Fabrics'
  • [2018] A Unified Hardware-Software MonitoringMethod for Reconfigurable Computing Architectures using PAPI
  • [2018] IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado
  • [2018] Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems
  • [2017] Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC
  • [2017] Cross-layer design of reconfigurable cyber-physical systems
  • [2017] Dynamic reconfiguration under RTEMS for fault mitigation and functional adaptation in SRAM-based SoPCs for space systems
  • [2017] Evaluating High-Level Synthesis Techniques for Scalable Hardware-Accelerated Computing
  • [2017] Evaluating High-Level Synthesis Techniques for Scalable Hardware-Accelerated Computing
  • [2016] Teaching Hybrid HW/SW Embedded System Design Using FPGA-Based Devices
  • [2015] A Self-Tuned Thermal Compensation System for Reducing Process Variation Influence in Side-Channel Attack Resistant Dual-Rail Logic
  • [2015] Design of OpenCL-Compatible Multithreaded Hardware Accelerators with Dynamic Support for Embedded FPGAs
  • [2015] Execution modeling in self-aware FPGA-based architectures for efficient resource management
  • [2015] Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs
  • [2015] Live Demonstration: A Dynamically Adaptable Image Processing Application Running in an FPGA-Based WSN Platform
  • [2014] A Dynamically Adaptable Image Processing Application Trading Off Between High Performance, Consumption and Dependability in Real Time
  • [2014] A Progressive Dual-Rail Routing Repair Approach for FPGA Implementation of Crypto Algorithm
  • [2014] A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems
  • [2014] A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor
  • [2014] Analysis of Design Alternatives on using Dynamic and Partial Reconfiguration in a Space Application
  • [2014] Collaborative Evolution Strategies on Evolvable Hardware Networked Elements
  • [2014] Development of Brain-Computer Interfaces using evolvable hardware
  • [2014] Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration
  • [2014] Increased fault tolerance in evolvable hardware through automatic upscaling
  • [2014] Power-aware multi-objective evolvable hardware system on an FPGA
  • [2013] A Noise-Agnostic Self-Adaptive Image Processing Applications Based on Evolvable Hardware
  • [2013] A Noise-Agnostic Self-Adaptive Image Processing Applications Based on Evolvable Hardware
  • [2013] A Novel FPGA-based Evolvable Hardware System based on Multiple Processing Arrays
  • [2013] A Novel FPGA-based Evolvable Hardware System based on Multiple Processing Arrays
  • [2013] A Scalable Evolvable Hardware Processing Array
  • [2013] A self-adaptive image processing application based on evolvable and scalable hardware
  • [2013] Architectural Evaluation of Dynamic and Partial Reconfigurable Systems designed with DREAMS Tool
  • [2013] Architectural Evaluation of Dynamic and Partial Reconfigurable Systems designed with DREAMS Tool
  • [2013] Hardening digital systems with distributed functionality: robust networks
  • [2013] Noise-agnostic Adaptive Image Filtering without Training References on an Evolvable Hardware Platform
  • [2013] Prospection of Reconfiguration Capabilities using Space Qualified SRAM-based FPGAs for a Satellite Communications Application
  • [2012] An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation
  • [2012] Automatic Generation of Identical Routing Pairs for FPGA Implemented DPL Logic
  • [2012] Dreams: A Tool for the design of Dynamically Reconfigurable Embedded and Modular Systems
  • [2012] FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels
  • [2012] Implementation techniques for evolvable HW systems: virtual vs. dynamic reconfiguration
  • [2012] Implementation techniques for evolvable HW systems: virtual vs. dynamic reconfiguration
  • [2012] Power Management Techniques in an FPGA-Based WSN Node for High Performance Application
  • [2011] "Scalable 2D architecture for H.264 SVC deblocking filter with reconfiguration capabilities for on-demand adaptation"
  • [2011] 2D Reconfigurable Systolic Core Architecture for Evolvable Systems
  • [2011] A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self- Adaptive Systems
  • [2011] A Novel Scalable Deblocking-Filter Architecture for H.264/AVC and SVC Video Codecs
  • [2011] A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations
  • [2011] A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations
  • [2011] Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs
  • [2011] De la reconfigurabilidad a las redes de sensores (y viceversa)
  • [2011] Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support
  • [2011] Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems
  • [2011] Framework adaptable y reconfigurable dinámicamente para procesamiento de vídeo: aplicación a la etapa de filtrado adaptativo en sistemas de compresión de vídeo H.264/AVC y SVC
  • [2011] Low-power, high-speed FFT processor for MB-OFDM UWB application
  • [2011] Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs
  • [2011] SCA security verification on wireless sensor network node
  • [2011] SCA security verification on wireless sensor network node
  • [2010] A Modular Peripheral to Support Self¿Reconfiguration in SoCs
  • [2010] Development of an aeronautical electromechanical actuator with real time health monitoring capability
  • [2010] Feasibility of HW genetic algorithms for profile selection in reconfigurable autonomous embedded systems
  • [2010] Generic Systolic Array for Run-time Scalable Cores
  • [2010] Run-time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs
  • [2009] Method for run time hardware code profiling for algorithm acceleration
  • [2009] NoC generation of an optimal memory distribution for multimedia systems
  • [2009] Reconfiguring Crypto Hardware Accelerators on Wireless Sensor Nodes
  • [2009] Using Partial Reconfiguration for SoC Design and Implementation
  • [2008] A Fast Emulation-Based NoC Prototyping Framework
  • [2008] NoC Emulation based on Partial Reconfiguration
  • [2008] Remote HW-SW Reconfigurable Wireless Sensor Nodes
  • [2008] Virtual Architectures for Partial Runtime Reconfigurable Systems. Application to Network on Chip based SoC Emulation
  • [2007] Creating partially reconfigurable systems
  • [2007] Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management
  • [2007] Space Design Exploration of a Viterbi-based ECC Encoding/Decoding Scheme by Wireless Transmission Emulation
  • [2007] Towards fine and medium grain dynamic functional extraction
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• Premios
  • [2017] Vector de oro: mejor profesor de la especialidad del Máster en Ingeniería Industrial
  • [2016] Premio al mejor trabajo de investigación del IRM 2016
  • [2012] Best Paper Award
  • [2012] Best paper award
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• Proyectos de I+D+i
  • [2019] INICIATIVA EUROPEA PARA FACILITAR LA VALIDACIÓN SISTEMAS SEGUROS Y ALTAMENTE AUTOMATIZADOS
  • [2019] INICIATIVA EUROPEA PARA FACILITAR LA VALIDACIÓN SISTEMAS SEGUROS Y ALTAMENTE AUTOMATIZADOS
  • [2019] PHD STUDY FOR SAFE RECONFIGURATION OF HARDWARE ACCELERATORS ON MULTI-FPGA PLATFORMS FOR SPACE APPLICATIONS
  • [2018] CARRYING OUT OF THALES ALENIA SPACE ESPAÑA YEAR ROUND CONTRACT FOR 2016-2017
  • [2018] DESARROLLO DE SOLUCIONES TIC INTEGRADAS PARA EL FOMENTO DE LA GESTIÓN URBANA, SOSTENIBLES Y RESILENTES (CITIZEN 2 CITIZEN)
  • [2018] ESA 2018-04: Co-sponsored PhD on: "Safe Reconfiguration of Hardware Accelerators on Multi-FPGA Platforms for Space Applications"
  • [2018] GORDON 2.0: DESARROLLO HERRAMIENTA SOFTWARE DE RESPUESTA EN TIEMPO REAL PARA OPTIMIZAR UNA FLOTA DE RECOGIDA SOSTENIBLE (GORDON 2.0)
  • [2018] INICIATIVA EUROPEA PARA FACILITAR LA VALIDACIÓN SISTEMAS SEGUROS Y ALTAMENTE AUTOMATIZADOS
  • [2018] PLATINO: Plataforma HW/SW distribuida para el procesamiento inteligente de información sensorial heterogénea en aplicaciones de supervisión de grandes espacios naturales
  • [2017] CARRYING OUT OF THALES ALENIA SPACE ESPAÑA YEAR ROUND CONTRACT FOR 2016-2017
  • [2017] CIRCUITS AND SYSTEM (CAS) DEL IEEE
  • [2017] CROSS-LAYER MODEL-BASED FRAMEWORK FOR MULTI-OBJECTIVE DESIGN OF RECONFIGURABLE SYSTEMS IN UNCERTAIN HYBRID ENVIRONMENTS
  • [2017] DESARROLLO DE SOLUCIONES TIC INTEGRADAS PARA EL FOMENTO DE LA GESTIÓN URBANA, SOSTENIBLES Y RESILENTES (CITIZEN 2 CITIZEN)
  • [2017] EUROPEAN INITIATIVE TO ENABLE VALIDATION FOR HIGLY AUTOMATED SAFE AND SECURE SYSTEMS (ENABLE) - S3
  • [2017] INICIATIVA EUROPEA PARA FACILITAR LA VALIDACIÓN SISTEMAS SEGUROS Y ALTAMENTE AUTOMATIZADOS
  • [2016] CROSS-LAYER MODEL-BASED FRAMEWORK FOR MULTI-OBJECTIVE DESIGN OF RECONFIGURABLE SYSTEMS IN UNCERTAIN HYBRID ENVIRONMENTS
  • [2016] DESARROLLO DE SOLUCIONES TIC INTEGRADAS PARA EL FOMENTO DE LA GESTIÓN URBANA, SOSTENIBLES Y RESILENTES (CITIZEN 2 CITIZEN)
  • [2016] ENABLE-S3: European Initiative to Enable Validation for Highly Automated Safe and Secure Systems
  • [2016] Enable-S3: Iniciativa Europea para facilitar la validación de sistemas seguros y altamente automatizados
  • [2016] INICIATIVA EUROPEA PARA FACILITAR LA VALIDACIÓN SISTEMAS SEGUROS Y ALTAMENTE AUTOMATIZADOS
  • [2015] DREAMS-UPM: Dynamically Reconfigurable embedded platforms for Networked Context-aware multimedia Systems-UPM
  • [2015] REBECCA: Sistemas electrónicos empotrados confiables para control de ciudades bajo situaciones atípicas
  • [2014] DISEÑO Y PROTOTIPADO DE UNA PLACA DE DESARROLLO Y CARACTERIZACIÓN DE APLICACIONES QUE SE IMPLEMENTEN EN UNA FGPA BASADA EN RAM
  • [2014] FastCUDA
  • [2013] DISEÑO Y PROTOTIPADO DE UNA PLACA DE DESARROLLO Y CARACTERIZACIÓN DE APLICACIONES QUE SE IMPLEMENTEN EN UNA FGPA BASADA EN RAM
  • [2013] RECONFIGURABLE ULTRA-AUTONOMOUS NOVEL ROBOTS RUNNER
  • [2012] DYNAMICALLY RECONFIGURABLE EMBEDDED PLATFORM FOR NETWARKED CONTEXT-AWARE MULTIMEDIA SYSTEMS-UPM
  • [2012] ENCLAVAMIENTO ELECTRÓNICO DE NUEVA GENERACIÓN. ENCE-NG
  • [2012] RECONFIGURABLE ULTRA-AUTONOMOUS NOVEL ROBOTS RUNNER
  • [2012] TECALUM - SISTEMA DE ILUMINACION INTELIGENTE
  • [2012] TECNOLOGIAS EFICIENTES E INTELIGENTES ORIENTADAS A LA SALUD Y AL CONFORT EN AMBIENTES INTERIORES.
  • [2011] Curso sobre Redes de Sensores Inalámbricas
  • [2011] DYNAMICALLY RECONFIGURABLE EMBEDDED PLATFORM FOR NETWARKED CONTEXT-AWARE MULTIMEDIA SYSTEMS-UPM
  • [2011] FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels
  • [2011] GIST: ICT Tools greening food processing businesses
  • [2011] PLATAFORMA TECNOLOGICA INTELIGENTE PRODUCCION SOSTENIBLE INDUSTRIAS AGROALIMENTARIAS.
  • [2011] PLATAFORMA TECNOLÓGICA INTELIGENTE PARA LA PRODUCCIÓN SOSTENIBLE EN INDUSTRIAS AGROALIMENTARIAS
  • [2011] RECONFIGURABILIDAD DINAMICA PARA ESCALABILIDAD EN REDES ORIENTADAS A APLICACIONES MULTIMEDIA
  • [2011] RECONFIGURABILIDAD INTEROPERABLE
  • [2011] RECONFIGURABLE ULTRA-AUTONOMOUS NOVEL ROBOTS RUNNER
  • [2011] SAFETYMINE
  • [2011] TECALUM - SISTEMA DE ILUMINACION INTELIGENTE
  • [2011] TECNOLOGIAS EFICIENTES E INTELIGENTES ORIENTADAS A LA SALUD Y AL CONFORT EN AMBIENTES INTERIORES.
  • [2011] WSN DEVELOPMENT, PLANNING AND COMMISIONING &MAINTENANCE TOOLSET
  • [2010] HEALTH MONITORING (DETECCI¿N PREVENTIVA DE FALLOS EN EQUIPOS ELECTROMEC¿NICOS DE VUELO.
  • [2010] PLATAFORMA TECNOLOGICA INTELIGENTE PRODUCCION SOSTENIBLE INDUSTRIAS AGROALIMENTARIAS.
  • [2010] PLATAFORMA TECNOLÓGICA INTELIGENTE PARA LA PRODUCCIÓN SOSTENIBLE EN INDUSTRIAS AGROALIMENTARIAS
  • [2010] RECONFIGURABILIDAD DINAMICA PARA ESCALABILIDAD EN REDES ORIENTADAS A APLICACIONES MULTIMEDIA
  • [2010] REDES DE SENSORES PARA PREVENCION CATASTROFES Y GESTION CRISIS EN TUNELES (TUNEL-CARE)
  • [2010] Reconfigurable Ultra-Autonomous Novel Robots
  • [2010] SAFETYMINE
  • [2010] SAFETYRAIL- SEGURIDAD EN VIAS FERROVIARIAS
  • [2010] SECURE, MOBILE VISUAL SENSOR NETWORKS ARCHI TECTURE (SMART)
  • [2010] SEGURIDAD EN VIAS FERROVIARIAS (SAFETYRAIL)
  • [2010] TECNOLOGIAS EFICIENTES E INTELIGENTES ORIENTADAS A LA SALUD Y AL CONFORT EN AMBIENTES INTERIORES.
  • [2010] TUNEL-CARE REDES DE SENSORES PARA PREVENCION DE CATRASTROFES Y GESTION DE CRISIS EN TUNELES
  • [2009] FPGAs para el PEM Unit Tester de GAIA CRf045 Y crf046.
  • [2009] HEALTH MONITORING (DETECCIÓN PREVENTIVA DE FALLOS EN EQUIPOS ELECTROMECÁNICOS DE VUELO.
  • [2009] INTEGRACIÓN HW/HW Y HW/SW PARA TECNOLOGÍA WSN.
  • [2009] PLATAFORMA TECNOLOGICA INTELIGENTE PRODUCCION SOSTENIBLE INDUSTRIAS AGROALIMENTARIAS.
  • [2009] REALIZACIÓN DE TU08
  • [2009] RECONFIGURABILIDAD DINAMICA PARA ESCALABILIDAD EN REDES ORIENTADAS A APLICACIONES MULTIMEDIA
  • [2009] REDES DE SENSORES PARA PREVENCION CATASTROFES Y GESTION CRISIS EN TUNELES (TUNEL-CARE)
  • [2009] SAFETYMINE
  • [2009] SAFETYRAIL- SEGURIDAD EN VIAS FERROVIARIAS
  • [2008] Ayudas a los grupos de I+D
  • [2008] Integración HW/HW para tecnología WSN
  • [2008] Plataforma tecnológica inteligente para la producción sostenible en industrias agroalimentarias
  • [2008] Realización de FPGAs para el PEM Unit Tester de GAIA CRF045 y CRF046
  • [2008] Realizaciónd de TU08
  • [2008] Reconfigurabilidad dinámica para escalabilidad en redes orientadas a aplicaciones multimedia
  • [2008] Redes de sensores para prevención de catástrofes y gestión de crisis en túneles
  • [2008] Requisitos Herramienta WSN
  • [2008] Secure, Mobile visual sensor networks ArchiTecture
  • [2008] Seguridad en minas y canteras basándose en redes de sensores inalámbricas
  • [2007] Análisis y modelado del consumo en redes de sensores (AMCORS)
  • [2007] Depuración y validación de SoCs basada en arquitecturas reconfigurables y NoCs (ENDIVIA-DEVASAR)
  • [2007] Estado del arte actuadores para WSN
  • [2007] Realización de FPGA para el test del sistema GAIA CRF041_GAIA_TEST (GAIA)
  • [2007] Requisitos Herramienta WSN (Requisitos_WSN)
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• Responsabilidades
  • [2017] General Chair de la conferencia ReCoSoC 2017
  • [2014] DCIS
  • [2012] Miembro de Comité de Programa de JCRA 2012 (Granada)
  • [2012] Miembro del Program Committee de RecoSoc 2012
  • [2012] Program Co-Chair del Congreso ReConFig 2012
  • [2012] Representante electo de Junta de Escuela
  • [2012] Revisor de DAC
  • [2012] Revisor de IECON
  • [2012] Revisor de IEEE Sensors Journal
  • [2012] Revisor de IEEE Transactions on Computers
  • [2012] Revisor de ISIE
  • [2012] Revisor de JCRA
  • [2012] Revisor de Journal on Reconfigurable Computing (Hindawi)
  • [2012] Revisor de ReCoSoc
  • [2012] Revisor de Transactions on Industrial Informatics
  • [2012] Revisor de artículos para el Student Contest del IEEE, sección 8
  • [2012] Track coordinator de la General Session de Reconfig 2012 (Cancún, Méjico)
  • [2009] Editores del VLSI Circuits and Systems IV
  • [2009] Program Chairman de VLSI Circuits and Systems IV
  • [2009] Revisor de artículos en IECON (Industrial Electronics Conference)
  • [2009] Revisor de artículos en ISIE (Int. Symposium on Industrial Electronics)
  • [2009] Revisor en revista IEEE Transactions on Industrial Electronics
  • [2008] Revisor de artículos en IECON (Industrial Electronics Conference)
  • [2008] Revisor de artículos en ISIE (Int. Symposium on Industrial Electronics)
  • [2008] Revisor en IEEE Transactions on Industrial Electronics
  • [2007] Subdirector del Departamento de Automática, Ingeniería Electrónica e Informática Industrial de la ETSII de la UPM
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• Tesis Doctorales
  • [2019] Architecture and methodology for automated development of evolvable and reconfigurable hardware applications
  • [2015] Parametric and structural self-adaptation of embedded systemsusing evolvable hardware
  • [2015] Run-Time dynamically adaptable fpga-based architecture forhigh-performance autonomous distributed systems
  • [2014] Run-Time Scalable Hardware for Reconfigurable Systems
  • [2014] Side-Channel Attack Protection Techniques In Fpga Y Systems Using Enhanced Dual-Rail Solutions
  • [2013] Implementation of an online signal processing system for a multidimensional ultrasound Doppler flow velocimeter by means of FPGAs
  • [2013] Noise-agnostic self-adaptive evolvable hardware for real time video filtering applications
  • [2009] Computación reconfigurable basada en FPGAs comerciales. Soluciones para el diseño e implementación de sistemas parcialmente reconfigurables
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