Portal de Transparencia

Actividad investigadora:

• Artículos en revistas
  • [2019] A 365mV, 13nW CMOS-only energy harvested reference voltage for RFID applications in 40nm technology
  • [2019] Temperature-aware writing architecture for multilevel memristive cells
  • [2018] A temperature variation tolerant CMOS-only voltage reference for RFID applications
  • [2018] Auto-Erasable RRAM Architecture Secured Against Physical and Firmware Attacks
  • [2018] Guest Editorial: Special Section on Fast Fourier Transform (FFT) Hardware Implementations
  • [2018] Performance-oriented Implementation of Hilbert Filters on FPGAs
  • [2018] Self-controlled multilevel writing architecture for fast training in neuromorphic RRAM applications
  • [2017] A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
  • [2017] Democratizing science with the aid of parametric design and additive manufacturing: Design and fabrication of a versatile and low-cost optical instrument for scattering measurement
  • [2017] On the Design and Analysis of Reliable RRAM-CMOS Hybrid Circuits
  • [2017] On the Design and Analysis of Reliable RRAM-CMOS Hybrid Circuits
  • [2017] Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges
  • [2016] A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
  • [2016] A Performance Study of CUDA UVM versus Manual Optimizations in a Real-World Setup: Application to a Monte Carlo Wave-Particle Event-Based Interaction Model
  • [2016] A Performance Study of CUDA UVM versus Manual Optimizations in a Real-World Setup: Application to a Monte Carlo Wave-Particle Event-Based Interaction Model
  • [2016] Calibration-free 1052 mu m(2) Power Supply Monitor
  • [2016] Characterization of Analog Modules: Reliability Analyses of Radiation, Temperature and Variations Effects
  • [2016] Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges.
  • [2016] Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges.
  • [2016] Reliable Design Methodology: The Combined Effect of Radiation, Variability and Temperature
  • [2016] Taxonomy of Power Supply Monitors and Integration Challenges
  • [2015] 2.64 pJ Reference-Free Power Supply Monitor with a Wide Temperature Range
  • [2015] A Dual-Layer Fault Manager for Systems based on Xilinx Virtex FPGAs
  • [2015] A Survey on Theoretical and Practical Aspects of Imaging Aids for Artificial Vision in Professional Environments
  • [2015] A Thermal Adaptive Scheme for Reliable Write Operation on RRAM Based Architectures
  • [2015] A time-resolved Monte Carlo smoke model for use at optical and infrared frequencies
  • [2015] An In-Depth Analysis of Ring Oscillators: Exploiting Their Configurable Duty-Cycle
  • [2015] Design and Characterization of a Built-In CMOS TID Smart Sensor
  • [2015] Evolution of Radiation-Induced Soft Errors in FinFET SRAMs under Process Variations beyond 22nm
  • [2015] Implementation of a Real-Time Spectrum Analyzer on FPGA Platforms
  • [2015] Implementation of a Real-Time Spectrum Analyzer on FPGA Platforms
  • [2015] Real-Time Low-Complexity Automatic Modulation Classifier for Pulsed Radar Signals
  • [2014] A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs)
  • [2014] A Tool for the Automatic Analysis of Single Events Effects on Electronic Circuits
  • [2014] Building Memristor Applications: From Device Model to Circuit Design
  • [2014] Four-Injector Variability Modeling of FinFET Predictive Technology Models
  • [2014] Real-time radar pulse parameter extractor
  • [2014] System Design Framework and Methodology for Xilinx Virtex FPGA Configuration Scrubbers
  • [2014] Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies
  • [2013] A 0.0016 mm(2) 0.64 nJ Leakage-Based CMOS Temperature Sensor
  • [2013] A 0.0016 mm(2) 0.64 nJ Leakage-Based CMOS Temperature Sensor
  • [2013] A Low-Area Reference-Free Power Supply Sensor
  • [2013] Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers
  • [2013] Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers
  • [2013] Floating-Point Exponentiation Units for Reconfigurable Computing
  • [2013] High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator
  • [2013] Ratio-Based Temperature-Sensing Technique Hardened Against Nanometer Process Variations
  • [2012] A Light-Weight On-Chip Monitoring Network for Dynamic Adaptation and Calibration
  • [2012] High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator
  • [2012] Improving Hardware Reuse through XML-based Interface Encapsulation
  • [2011] A Light-Weight On-Chip Monitoring Network for Dynamic Adaptation and Calibration
  • [2011] Customizing floating-point units for FPGAs: Area-performance-standard trade-offs
  • [2011] Customizing floating-point units for FPGAs: Area-performance-standard trade-offs
  • [2011] Customizing floating-point units for fpgas: Area-performance-standard trade-offs
  • [2010] Thermal analysis and modeling of embedded processors
  • [2010] Thermal analysis and modeling of embedded processors
  • [2008] A Nanowatt Smart Thermal Sensor for Dynamic Temperature Management
  • [2008] A hardware mechanism to reduce the energy consumption of the register file of in-order architectures
  • [2008] Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio
  • [2008] Implementing FFT-Based Digital Channelized Receivers on FPGA Platforms
  • [2008] Implementing FFT-based digital channelized receivers on FPGA platforms
  • [2008] Joint hardware¿software leakage minimization approach for the register file of VLIW embedded architectures
  • [2008] Power Considerations in Banked CAMs: A leakage Reduction Approach
  • [2007] Energy-Aware Compilation and Hardware Design for VLIW Embedded Systems
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• Capítulos de libros
  • [2012] Temperature Monitoring Issues in Nanometer CMOS Integrated Circuits
  • [2012] Temperature Monitoring Issues in Nanometer CMOS Integrated Circuits.
  • [2009] SoC Communication Architectures: From Interconnection Buses to Packet-Switched NoCs
  • [2007] Joint Source-Channel Decoding ASIP Architecture for Sensor Networks
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• Conferencias invitadas en congresos
  • [2019] A 365mV, 13nW CMOS-only energy harvested reference voltage for RFID applications in 40nm technology
  • [2018] Bringing emerging technologies into the real world
  • [2017] Robust design based on variability monitoring
  • [2013] DCIS 2013 Special Session. Variability and Reliability
  • [2012] Monitoring: a lifeboat in a varying environment
  • [2010] System-on-Chip monitoring networks targeting nanometer technologies
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• Creación de empresas
  • [2010] SPEEDUP Systems España, Sociedad Limitada
• Cursos, seminarios y tutoriales
  • [2015] On-chip PVT Variation Monitoring
• Estancias y sabáticos recogidos en programas oficiales
  • [2019] Estancia de investigación en MIT
  • [2018] Design of advanced digital circuits with GaN technology
  • [2017] Estancia en el MIT (EEUU)
  • [2016] Sabático en MIT (EEUU), grupo del Prof. A. Chandrakasan
  • [2015] Sabático en el MTL (MIT) 2015-2016
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• Otros méritos
  • [2017] Editor de special issue on 'Fast Fourier transform (FFT) Hardware Implementations'
  • [2017] Revisor Electronics Letters
  • [2017] Revisor Journal of Parallel and Distributed Computing
  • [2017] Vocal del centro de investigación IPTC
  • [2012] Member of the EDAA Best 2012 PhD Dissertation Award
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• Patentes
  • [2009] Aparato para la medida de temperatura y corriente de fugas en un chip
  • [2008] Aparato para la medida de temperatura y corriente de fugas en un chip
  • [2008] Procedimiento y arquitectura electrónica para la detección SOVA óptima basado en el rastreo de puntos de fusión
  • [2007] Aparato para la medida de temperatura y corriente de fugas en un chip
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• Ponencia en Congresos
  • [2019] Temperature-aware writing architecture for multilevel memristive cells
  • [2018] Performance-oriented Implementation of Hilbert Filters on FPGAs
  • [2017] Advanced integration of variability and degradation in RRAM SPICE compact models
  • [2017] CAS-T Lecture: Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges
  • [2017] CAS-T Lecture: SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds
  • [2016] A temperature-independent PUF with a configurable duty cycle of CMOS ring oscillators
  • [2016] Calibration-free 1052 µm2 power supply monitor
  • [2016] Characterization of analog modules: Reliability analyses of radiation, temperature and variations effects
  • [2016] Reliable Design Methodology: The Combined Effect of Radiation, Variability and Temperature
  • [2016] Taxonomy of Power Supply Monitors and Integration Challenges
  • [2015] A Dual-Layer Fault Manager for Systems based on Xilinx Virtex FPGAs
  • [2015] A Thermal Adaptive Scheme for Reliable Write Operation on RRAM Based Architectures
  • [2015] Evolution of Radiation-Induced Soft Errors in FinFET SRAMs under Process Variations beyond 22nm
  • [2015] Evolution of Radiation-Induced Soft Errors in FinFET SRAMs under Process Variations beyond 22nm
  • [2014] A built-in CMOS Total Ionization Dose smart sensor
  • [2014] A tool for the automatic analysis of single events effects on electronic circuits
  • [2014] Four-injector variability modeling of FinFET predictive technology models
  • [2014] Implementation tradeoffs of triangle traversal algorithms for graphics processing
  • [2014] Real-time radar pulse parameter extractor
  • [2013] A Low-Area Reference-Free Power Supply Sensor
  • [2013] Improvement of Radar Capabilities by Reconfigurable Digital Signal Processing
  • [2012] A CAD framework for the characterization and use of memristor models
  • [2012] A Monitoring Infrastructure for FPGA Self-Awareness and Dynamic Adaptation
  • [2012] Design and Implementation of Floating-Point FFT Architectures for FPGA Devices
  • [2012] Hardware Reuse Improvement through the Domain Specific Language dHDL
  • [2012] Hardware Reuse Improvement through the Domain Specific Language dHDL.
  • [2012] Improving Hardware Reuse through XML-based Interface Encapsulation
  • [2012] Temperature Sensor Placement Including Routing Overhead and Sampling Inaccuracies
  • [2011] Area-Efficient Linear Regression Architecture for Real-Time Signal Processing on FPGAs
  • [2011] Area-delay Trade-offs of Texture Decompressors for a Graphics Processing Unit
  • [2011] Assesing Self-Learning Electronics through the Support of Remote Labs
  • [2011] Cycle-Accurate Configuration Layer Model for Xilinx Virtex FPGAs
  • [2011] FPGA Acceleration of Monte Carlo-based Financial Simulation: Design Challenges and Lessons Learnt
  • [2011] FPGA acceleration of Monte Carlo-based financial simulation: Design challenges and lessons learnt
  • [2011] ON-CHIP MONITORING: A LIGHT-WEIGHT INTERCONNECTION NETWORK APPROACH
  • [2011] On-chip Monitoring: A Light-Weight Interconnection Network Approach
  • [2011] Real Time FPGA Implementation of an Modulation Classifier for Electronic Warfare Applications
  • [2011] Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs
  • [2010] Design of an Efficient Interconnection Network of Temperature Sensors
  • [2010] On the Hardware Implementation of Triangle Traversal Algorithms for Graphics Processing
  • [2009] Development of a standard single floating-point library and its encapsulation for reuse
  • [2009] Exploring Performance-Power Trade-offs for Look-Up Tables in SRAM-based FPGAs
  • [2009] Providing Self-learning to Students of Highly Attended Electronics Courses through the Remote Access to a Microelectronics Laboratory
  • [2008] A Novel Small Low-Power Interface for On-Chip Thermal Sensors
  • [2008] A Web-based Environment Providing Remote Access to FPGA Platforms for Teaching Digital Hardware Design
  • [2008] An FPGA Implementation of the Powering Function with Single Precision Floating-Point Arithm
  • [2008] An FPGA Run-Time Parameterisable Log-Normal Random Number Generator
  • [2008] Docencia Semipresencial en Laboratorios Docentes para Diseño de Hardware Digital en la ETSIT-UPM
  • [2008] Experimental Methodology for Power Characterization of FPGAs
  • [2008] Variance reduction techniques for Monte Carlo simulations. A parameterizable FPGA approach
  • [2007] Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems
  • [2007] FPGA Gaussian Random Number Generator Based on Quintic Hermite Interpolation Inversion
  • [2007] Leakage-based On-Chip Thermal Sensor for CMOS Technology
  • [2007] Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors
  • [2007] Thermal Analysis of the Shared Register File in VLIW Architectures.
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• Premios
  • [2018] Premio extraordinario de doctorado (Fernando García)
  • [2009] Primer premio en la VII Competición de Creación de Empresas de la UPM
• Proyectos de I+D+i
  • [2019] Desarrollo Algoritmo Mod Intrapulso
  • [2019] NEUROWARE: Efficient and Robust Hardware for Brain-Inspired Computin
  • [2019] VARIABILIDAD EN TECNOLOGIAS NANOMETRICAS: TOLERANCIA, FIABILIDAD Y APROVECHAMIENTO (TOLERA-2)
  • [2019] Variability in Nanometric technologies: Tolerance, Reliability and Benefits
  • [2018] Desarrollo Algoritmo Mod Intrapulso
  • [2018] SOPORTE A LA DEFINICIÓN, DISEÑO, DESARROLLO Y VALIDACIÓN DE UNA BIBLIOTECA MICROELECTRÓNICA DE CÉLULAS ESTÁNDAR ENDURECIDA FRENTE A RADIACIÓN, COMPATIVLE CON LA TECNOLOGÍA IHP SGB25RH
  • [2018] VARIABILIDAD EN TECNOLOGIAS NANOMETRICAS: TOLERANCIA, FIABILIDAD Y APROVECHAMIENTO (TOLERA-2)
  • [2017] SOPORTE A LA DEFINICIÓN, DISEÑO, DESARROLLO Y VALIDACIÓN DE UNA BIBLIOTECA MICROELECTRÓNICA DE CÉLULAS ESTÁNDAR ENDURECIDA FRENTE A RADIACIÓN, COMPATIVLE CON LA TECNOLOGÍA IHP SGB25RH
  • [2017] TOLERANCIA A VARIACIONES PVT Y RADIACIÓN EN TECNOLOGÍAS NANOMETRICAS
  • [2017] VARIABILIDAD EN TECNOLOGIAS NANOMETRICAS: TOLERANCIA, FIABILIDAD Y APROVECHAMIENTO (TOLERA-2)
  • [2016] SOPORTE A LA DEFINICIÓN, DISEÑO, DESARROLLO Y VALIDACIÓN DE UNA BIBLIOTECA MICROELECTRÓNICA DE CÉLULAS ESTÁNDAR ENDURECIDA FRENTE A RADIACIÓN, COMPATIVLE CON LA TECNOLOGÍA IHP SGB25RH
  • [2016] TOLERA-2: Variabilidad en tecnologías nanométricas: tolerancia, fiabilidad y aprovechamiento
  • [2016] TOLERANCIA A VARIACIONES PVT Y RADIACIÓN EN TECNOLOGÍAS NANOMETRICAS
  • [2016] VARIABILIDAD EN TECNOLOGIAS NANOMETRICAS: TOLERANCIA, FIABILIDAD Y APROVECHAMIENTO (TOLERA-2)
  • [2015] RADHARQ: DESARROLLO DE TECNOLOGÍA RESISTENTE A LA RADIACIÓN PARA MICROELECTRONICA ESPACIAL
  • [2015] TOLERA: Tolerancia a variaciones PVT y radiación en tecnologías nanométricas
  • [2014] BASYLIS
  • [2014] BASYLIS
  • [2014] RADHARQ: DESARROLLO DE TECNOLOGÍA RESISTENTE A LA RADIACIÓN PARA MICROELECTRONICA ESPACIAL
  • [2014] TOLERANCIA A VARIACIONES PVT Y RADIACIÓN EN TECNOLOGÍAS NANOMETRICAS
  • [2013] BASYLIS
  • [2013] RADHARQ: DESARROLLO DE TECNOLOGÍA RESISTENTE A LA RADIACIÓN PARA MICROELECTRONICA ESPACIAL
  • [2013] RED ESPAÑOLA DE VARIABILIDAD EN TECNOLOGIAS, CIRCUITOS Y SISTEMAS MICRO/NANOELECTRONICOS
  • [2013] TOLERANCIA A VARIACIONES PVT Y RADIACIÓN EN TECNOLOGÍAS NANOMETRICAS
  • [2011] DISEÑO ELECTRONICO AVANZADO: CONSULO, TEMPERATURA Y ALTAS PRESTACIONES
  • [2011] ESTUDIO Y DESARROLLO DE SISTEMAS DE GUERRA ELECTRONICA
  • [2010] ANÁLISIS E INVESTIGACIÓN DE ACELERACIÓN DE VALORACIÓN FINANCIERA MEDIANTE PLATAFORMAS RECONFIGURABLES.
  • [2010] DISEÑO ELECTRONICO AVANZADO: CONSULO, TEMPERATURA Y ALTAS PRESTACIONES
  • [2010] ESTUDIO Y DESARROLLO DE SISTEMAS DE GUERRA ELECTRONICA
  • [2010] OPTIMIZACION DE CONSUMO Y TEMPERATURA EN ARQUITECTURAS COMPLEJAS
  • [2009] ANÁLISIS E INVESTIGACIÓN DE ACELERACIÓN DE VALORACIÓN FINANCIERA MEDIANTE PLATAFORMAS RECONFIGURABLES.
  • [2009] ARQUITECTURA DIGITALES DE ALTAS PRESTACIONES
  • [2009] ESTUDIO Y DESARROLLO DE SISTEMAS DE GUERRA ELECTRONICA
  • [2009] ESTUDIO Y DESARROLLO DE SISTEMAS DE GUERRA ELECTRÓNICA.
  • [2009] Optimización de consumo y temperatura en arquitecturas complejas
  • [2008] Arquitecturas Digitales de Altas Prestaciones
  • [2008] Estudio y Desarrollo de Sistemas de Guerra Electrónica
  • [2008] OPTIMA: Optimización de Consumo y Temperatura en Arquitecturas Complejas
  • [2007] ANÁLISIS E INVESTIGACIÓN DE ACELERACIÓN DE VALORACIÓN FINANCIERA MEDIANTE PLATAFORMAS RECONFIGURABLES
  • [2007] OPTIMA: Optimización de Consumo y Temperatura en Arquitecturas Complejas (TEC2006-00739)
  • [2007] Sistemas Integrados para Entornos Inteligentes (SINTEI-2)
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• Responsabilidades
  • [2019] Associate Editor IEEE Trans. on Nanotechnology
  • [2019] DCIS Conference Steering Committee
  • [2019] EU Project Reviewer
  • [2019] Member of the Executive Committee of DATE Conference 2020
  • [2019] Member of the Program Committee of ISLPED Conference 2019
  • [2019] Program Chair of PATMOS 2019
  • [2019] Special Issue Editor in "Integration, the VLSI Journal"
  • [2018] Associate Editor, IEEE Transactions on Nanotechnology
  • [2018] DCIS Steering Committee member
  • [2018] Evaluación de proyectos europeos H2020-CS2
  • [2018] NANOARCH Conference TPC member
  • [2018] PATMOS 2018 Conference General Chair
  • [2018] Vocal del equipo directivo del Centro de Investigación IPTC
  • [2017] Associate Editor IEEE Trans. on Nanotechnology
  • [2017] Exhibition Theatre Co-chair Design Automation and Test in Europe (DATE) Conference
  • [2017] Miembro del Steering Committee del congreso DCIS 2017
  • [2016] Miembro de DATE'16 Program Committee
  • [2016] Miembro de DATE'17 Executive Committee
  • [2016] Miembro de DCIS'16 Steering Committee
  • [2016] Miembro de GLSVLSI'16 Program Committee
  • [2016] Miembro de ICCD'16 Program Committee
  • [2015] Member of the DCIS Steering Committee (XXX Conference on Design of Circuits and Integrated Systems)
  • [2015] Miembro del comité de programa DATE 2015
  • [2015] Miembro del comité de programa GLSVLSI 2015
  • [2015] Miembro del comité de programa ICCD 2015
  • [2015] Subdirectora para Planificación y Ordenación Académica
  • [2014] Member of the DCIS Steering Committee (XXIX Conference on Design of Circuits and Integrated Systems)
  • [2013] (2013 Miembros del Steering Committe y Revisores del congreso 28th Conference on Design of Circuits and Integrated Systems (DCIS 2013)
  • [2013] Revisde la revista IEEE Trans. on Circuits and Systems IIor
  • [2013] Revisor de la revista IEEE Trans. on Circuits and Systems I
  • [2013] Revisor de la revista IEEE Trans. on Components, Packaging and Manufacturing Technology
  • [2013] Revisor de la revista IEEE Transactions on Very Large Scale Integration Systems
  • [2013] TPC member DATE 13 (D4 Track co-chair)
  • [2013] TPC member Great Lake Symposium on VLSI
  • [2012] DATE 2012 - Member of the Technical Program Committee
  • [2012] DCIS (Conference on Design of Circuits and Integrated Systems)
  • [2012] GLSVLSI 2012 Member of the Technical Program Committee
  • [2012] Revisor IEEE Transactions on Industrial Informatics
  • [2012] Revisor IEEE Transactions on Very Large Scale Integration
  • [2012] Revisor Transactions on Components, Packaging and Manufacturing Technology
  • [2011] Miembro DCIS Steering Committee
  • [2011] Miembro comité de programa DATE Conference 2011
  • [2011] Miembro comité de programa Great Lake Symposium VLSI 2011
  • [2010] Conference on Design of Circuits and Integrated Systems (DCIS)
  • [2010] Miembro comisón selección proyectos CICYT 2010
  • [2010] Miembro comité de Programa DATE Conference
  • [2009] Comité de programa de DATE Conference
  • [2009] Programas de Postgrado y Doctorado - Departamento de Ingeniería Electrónica - ETSI Telecomunicación (UPM)
  • [2009] Revista IEEE Trans. on Computers
  • [2009] XXV Conference on Design of Circuits and Integrated Systems (DCIS 09)
  • [2009] XXV Conference on Design of Circuits and Integrated Systems (DCIS 09)
  • [2008] IEEE Transactions on Computers
  • [2008] Programas de Postgrado y Doctorado - Departamento de Ingeniería Electrónica - ETSI Telecomunicación (UPM)
  • [2008] XXIV Conference on Design of Circuits and Integrated Systems (DCIS 08)
  • [2007] Member of the Advisory Committee
  • [2007] Revisora de Revista
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• Tesis Doctorales
  • [2017] Modeling and design of ring oscillators and their application in radiation environments.
  • [2017] Resistive RAM: simulation and modeling for reliable design
  • [2017] Study, design and validation of a framework model for smoke and particle-filled atmospheres
  • [2015] Design and Simulation of Deep Nanometer SRAM Cells under Energy, Mismatch, and Radiation Constraints
  • [2015] Fault management techniques for systems with SRAM-based FPGAs.
  • [2012] Implementación de algoritmos de procesado de señal sobre FPGA: Especificación, Reutilización y Exploración del espacio de diseño
  • [2012] On-Chip Thermal Monitoring: Design, Placement and Interconnection of Temperature Sensors
  • [2011] HARDWARE ACCELERATION OF MONTE CARLO-BASED SIMULATIONS
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