Portal de Transparencia

Actividad investigadora:

• Artículos en revistas
  • [2019] High-performance Decoding of Variable-length Memory Data Packets for FPGA Stream Processing
  • [2019] Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs
  • [2018] Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs
  • [2016] Acceleration of Simulation-based Techniques for Fixed-point Word-length Selection in DSP Systems
  • [2016] Dynamic range and round-off noise estimation of fixed-point systems with control-flow structures
  • [2016] Scalable Modelling of the Fixed-point Round-off Noise through Automatic Clustered Noise Injection
  • [2015] A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors
  • [2014] Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits
  • [2014] Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes
  • [2012] A Reduced Complexity Scheme for Carrier Frequency Synchronization in Uplink 802.16e OFDMA
  • [2012] A complete dynamic power estimation model for data-paths in FPGA DSP designs
  • [2012] A reduced complexity scheme for carrier frequency synchronization in uplink 802.16e OFDMA
  • [2012] EVALUATION OF RAPID PROTOTYPING SOLUTIONS FOR A 802.16D FREQUENCY OFFSET ESTIMATION SCHEME
  • [2012] Evaluation of Rapid Prototyping Solutions for a 802.16d Frequency Offset Estimation Scheme
  • [2010] A Multi-Standard Frequency Offset Synchronization Scheme for 802.11n, 802.16d, LTE and DVB-T/H Systems
  • [2010] Improved Schemes for Tracking Residual Frequency Offset in DVB-T Systems
  • [2010] Power Estimation of Embedded Multiplier Blocks in FPGAs
  • [2010] SQNR Estimation of Fixed-Point DSP Algorithms
  • [2010] Triple-bit method for power estimation of nonlinear digital circuits in FPGAs
  • [2010] User Profiling in FPGA for Intrusion Detection Systems
  • [2009] Architectural Synthesis of Fixed-Point DSP Datapaths
  • [2008] Fast and Accurate Computation of the Round-Off Noise of LTI Systems
  • [2008] Fast and Accurate Power Estimation of FPGA DSP Components Based on High-level Switching Activity Models
  • [2007] FPGA Acceleration for DNA Sequence Alignment
  • [2007] Improved Interval-Based Characterization of Fixed-Point LTI Systems with Feedback Loops
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• Capítulos de libros
  • [2012] Design and Implementation of Hardware Modules for Baseband Processing in Radio Transceivers: A Case Study
  • [2012] Fast Fixed-Point Optimization of DSP Algorithms
  • [2012] Frequency Synchronization for OFDM/OFDMA Systems
  • [2011] Applications of Interval-Based Simulations to the Analysis and Design of Digital LTI Systems
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• Conferencias invitadas en congresos
  • [2012] Turning Control-flow Graphs into Callgraphs - Transformation of Partitioned Codes for Execution in Heterogeneous Architectures
• Cursos, seminarios y tutoriales
  • [2012] Turning Control-flow Graphs into Callgraphs - Transformation of Partitioned Codes for Execution in Heterogeneous Architectures
• Informes para las AAPP o sus organismos dependientes
  • [2013] Proposal for the Study, Prototyping and Design of the SKA Central Signal Processing Element
• Libros
  • [2017] Problemas de Sistemas Digitales con el Microcontrolador ColdFire 5272
  • [2009] Diseño de Sistemas Digitales con el microcontrolador ColdFire 5272
• Otras Publicaciones
  • [2014] Spanish Participation in the CSP Consortium
• Otros méritos
  • [2017] Revisor de IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • [2017] Revisor de Microprocessors & Microsystems: Embedded Hardware Design
  • [2016] Revisor de Journal of Systems Architecture
  • [2010] FastCFD. Desarrollo de técnicas avanzadas para aceleración de las simulaciones CFD para aplicaciones aeronáuticas
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• Patentes
  • [2016] Systems and Methods for Improving the Execution of Computational Algorithms
  • [2016] Systems and methods for improving the execution of computational algorithms
  • [2011] Systems and Methods for Improving the Execution of Computational Algorithms
  • [2011] Systems and Methods for Improving the Execution of Computational Algorithms
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• Ponencia en Congresos
  • [2019] High-performance Decoding of Variable-length Memory Data Packets for FPGA Stream Processing
  • [2018] Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs
  • [2016] Interval-based Analysis and Word-length Optimization of Non-linear Systems with Control-flow Structures
  • [2012] A Fast Interpolative Wordlength Optimization Method for DSP Systems
  • [2012] Acceleration of Monte-Carlo Simulation-based Quantization of DSP Systems
  • [2012] TBT Signal Model for Improved Accuracy of High-level Dynamic Power Estimation Procedure
  • [2012] Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures
  • [2012] Use of Multisine Excitations for Frequency-response Measurement of Nonlinear DC-DC Switching Converters
  • [2011] Interdependency of Fixed-Point Optimization and Architectural Synthesis for Reconfigurable Devices
  • [2011] Power Estimation of Dividers Implemented in FPGAs
  • [2010] Adaptive Identification of Nonlinear Multiple-Input Multiple-Output Systems Based on Volterra Models
  • [2010] Adaptive Identification of Nonlinear Multiple-Input Multiple-Output Systems Based on Volterra Models
  • [2010] Architectural Synthesis of DSP Circuits under Simultaneous Error and Time Constraints
  • [2010] Fast Fixed-Point Optimization of DSP Algorithms
  • [2010] Fast and accurate frequency offset tracking scheme for OFDM DVB-T Standard
  • [2010] Precision-Wise Architectural Synthesis of DSP Circuits
  • [2010] SQNR Estimation of Non-Linear Fixed-Point Algorithms
  • [2009] A Practical Method for Testing High-speed Networking Hardware Architectures
  • [2009] Análisis de viabilidad de la implementación de algoritmos CFD en plataformas hardware reconfigurables
  • [2009] Behavioural Biometrics Hardware Based on Bioinformatics Matching
  • [2009] Floorplan-based FPGA Interconnect Power Estimation in DSP Circuits
  • [2008] A Comparison of Approaches for High-Level Power Estimation of LUT-based DSP Components
  • [2008] A Methodology for CFD Acceleration through Reconfigurable Hardware
  • [2008] Analytical High-level Power model for LUT-based Components
  • [2008] Optimized Architectural Synthesis of Fixed-Point Datapaths
  • [2007] A Comparison of Frequency Offset Synchronization Algorithms for WiMAX OFDM Systems
  • [2007] A Novel Carrier Frequency Synchronization for WiMAX OFDM Systems
  • [2007] A TCP/IP Fragmentation Monitoring Core for Intrusion Prevention
  • [2007] Adding Value to TCP/IP Based Information Exchange Security on Specialised Hardware
  • [2007] Comparative Evaluation of Carrier Frequency Offset Tracking Schemes for WiMAX OFDM Systems
  • [2007] High-level Switching Activity Models for Multipliers in FPGAs
  • [2007] Switching Activity Models for Power Estimation in FPGA Multipliers
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• Proyectos de I+D+i
  • [2019] AMIGA 7. Entornos Extremos de Galaxias con los Precursores de SKA ? Desde el Diseño del Flujo de Datos hacia su Construcción ? Procesado de Datos en Hardware
  • [2019] AMIGA7: Entornos extremos de galaxias con los precursores de SKA - Desde el diseño del flujo de datos hacia su construcción - Procesado de datos en hardware
  • [2017] Red de Excelencia para la participación científica y tecnológica española en el SKA
  • [2016] AMIGA6
  • [2016] AMIGA6: Gas en el interior y en el entorno de las galaxias, Preparación científica para SKA y contribución al diseño del flujo de datos - Procesado de datos en hardware
  • [2016] REALIZACIÓN DE UN DISEÑO PARA COMUNICACIÓN SERIE DE MUY ALTA VELOCIDAD UTILIZANDO LOS TRANSCEIVERS DE LAS FPGAS KINTEX-7 DE XILINX
  • [2015] AMIGA5: El gas en las galaxias y en su entorno. Preparación científica y tecnológica para el SKA Procesado de datos en hardware
  • [2015] APPLICATION OF THE MULTISINE SIGNAL TO OBTAIN THE FREQUENCY RESPONSE WITH PSIM
  • [2015] REALIZACIÓN DE UN DISEÑO PARA COMUNICACIÓN SERIE DE MUY ALTA VELOCIDAD UTILIZANDO LOS TRANSCEIVERS DE LAS FPGAS KINTEX-7 DE XILINX
  • [2014] APPLICATION OF THE MULTISINE SIGNAL TO OBTAIN THE FREQUENCY RESPONSE WITH PSIM
  • [2012] DISEÑO DE UN SISTEMA DE PROCESAMIENTO DIGITAL DE SEÑAL PARA LA OPTIMIZACIÓN DE MEDIDAS EN ENTORNOS DE FUSIÓN
  • [2012] Proyecto AVANZA Competitividad I+D+I CORESIMULAERO
  • [2011] PEDIDO A8213093 G
  • [2011] PROYECTO CORESIMULAERO
  • [2011] RAVEN10: Design of Extremely Energy-Efficient Multi-Core Processor in Nanoscale CMOS for Media Processing in Portable Devices
  • [2011] SISTEMAS UWB MULTIELEMENTO Y RECONFIGURABLES PARA APLICACIONES AVANZADAS DE SEÑAL: DISEÑO MICROELECTRONICO
  • [2010] PEDIDO A8213093 G
  • [2010] SISTEMAS UWB MULTIELEMENTO Y RECONFIGURABLES PARA APLICACIONES AVANZADAS DE SEÑAL: DISEÑO MICROELECTRONICO
  • [2009] ARQUITECTURA DIGITALES DE ALTAS PRESTACIONES
  • [2009] EC FP6/IST 027095 - FASTMATCH.-
  • [2009] PEDIDO A8213093 G
  • [2009] SISTEMAS UWB MULTIELEMENTO Y RECONFIGURABLES PARA APLICACIONES AVANZADAS DE SEÑAL: DISEÑO MICROELECTRONICO
  • [2009] TELMAX EN EL MARCO DEL PROGRAMA CENIT 2006
  • [2009] TRANSCEPTORES MULTIELEMENTO Y MONOCIRCUITO PARA RADIOCOMUNICACION MULTIMEDIA DE BANDA ANCHA Y MUY ANCHA - DISEÑO MICROELECTRONICO
  • [2008] AMEBA 3: Transceptores Integrados Multielemento y Monocircuito para Radiocomunicación Digital de Banda Ancha y Muy Ancha. Diseño Electrónico
  • [2008] Arquitecturas Digitales de Altas Prestaciones
  • [2008] DOVRES.Design Optimization by Virtual Reality Simulation.
  • [2008] Proyecto de colaboración TELMAX
  • [2008] SERVIENDO: Servicios avanzados para personas con problemas de movilidad y comunicación
  • [2007] AMEBA 3. Transceptores Multielemento y Monocircuito para Radiocomunicación Multimedia de Banda Ancha y Muy Ancha - Diseño Microelectrónico
  • [2007] FASTMATCH: Framework Architecture to Semantically Integrate Advanced Thread Detection and Security Protection at Ultra-High Speeds
  • [2007] Segur@
  • [2007] Sistemas Integrados para Entornos Inteligentes (SINTEI-2)
  • [2007] Tempus CD-JEP-41107-2006
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• Responsabilidades
  • [2014] Revisor de la revista EURASIP Journal on Advances in Signal Processing
  • [2013] Revisor de la revista EURASIP Journal on Advances in Signal Processing
  • [2013] Revisor de la revista IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • [2013] Revisor de la revista Integration, The VLSI Journal
  • [2012] Revisor de la revista IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • [2011] Revisor de IET Circuits, Devices & Systems
  • [2011] Revisor de Integration, The VLSI Journal
  • [2008] Eurasip Journal of Embedded Systems, Hindawi Publishing, 2008
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• Tesis Doctorales
  • [2017] Compiler and Runtime Support for the Execution of Scientific Codes on Heterogeneous Parallel Architectures
  • [2016] Automated Word-length Optimization Framework for Multi-source Statistical Interval-based Analysis of Non-linear Systems with Control-flow Structures (Autor: Enrique Sedano Algarabel)
  • [2011] Optimización algorítmica orientada a la implementación en dispositivos reconfigurables de esquemas multiestándar y multiusuario para sincronismo de frecuencia en sistemas de comunicaciones inalámbricas basados en OFDM.
  • [2009] High-Level Power Estimation of DSP Circuits Implemented in FPGAs
  • [2008] Combined Word-Length Allocation and High-Level Synthesis of Digital Signal Processing Circuits.
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